Commit 2be86abc authored by Davide Giovanelli's avatar Davide Giovanelli
Browse files

Allining this repository with official CONTIKI-NG commit: 4464c893b32a5297835bc265068c8d63dc4ce00b

parent 363a0b2b
# -*- makefile -*-
#
# GCC specific definitions and actions
#
GCC_MAJOR_VERSION := $(shell $(CC) -v 2>&1 | grep "gcc version" | cut -b 13)
GCC_MINOR_VERSION := $(shell $(CC) -v 2>&1 | grep "gcc version" | cut -b 15)
# Warn if using version 6.3.x of arm-none-eabi-gcc
ifeq ("$(CC)","arm-none-eabi-gcc")
ifeq (6,$(GCC_MAJOR_VERSION))
ifeq (3,$(GCC_MINOR_VERSION))
$(warning Warning: you're using a version of $(CC) that may create broken Contiki-NG executables.)
$(warning We recommend to upgrade or downgrade your toolchain.)
endif
endif
endif
# Warn if using 4.6.x or older msp430-gcc
ifeq ("$(CC)","msp430-gcc")
ifeq ($(shell test $(GCC_MAJOR_VERSION) -lt 5; echo $$?),0)
ifeq ($(shell test $(GCC_MINOR_VERSION) -lt 7; echo $$?),0)
$(warning Warning: you're using an old version of $(CC).)
$(warning Upgrade to 4.7.x is recommended for extended memory support and bugfixes.)
endif
endif
endif
...@@ -39,7 +39,11 @@ endif ...@@ -39,7 +39,11 @@ endif
BUILD_DIR = build BUILD_DIR = build
BUILD_DIR_TARGET = $(BUILD_DIR)/$(TARGET) BUILD_DIR_TARGET = $(BUILD_DIR)/$(TARGET)
BUILD_DIR_BOARD = $(BUILD_DIR_TARGET)/$(BOARD)/$(BUILD_DIR_CONFIG) BUILD_DIR_TARGET_BOARD = $(BUILD_DIR_TARGET)/$(BOARD)
# If BOARD was empty, make sure we don't end up with a sequence of slashes
BUILD_DIR_FULL = $(BUILD_DIR_TARGET_BOARD:/=)/$(BUILD_DIR_CONFIG)
# Ditto if BUILD_DIR_CONFIG was empty
BUILD_DIR_BOARD = $(BUILD_DIR_FULL:/=)
OBJECTDIR = $(BUILD_DIR_BOARD)/obj OBJECTDIR = $(BUILD_DIR_BOARD)/obj
CONTIKI_NG_TARGET_LIB = $(BUILD_DIR_BOARD)/contiki-ng-$(TARGET).a CONTIKI_NG_TARGET_LIB = $(BUILD_DIR_BOARD)/contiki-ng-$(TARGET).a
...@@ -65,7 +69,7 @@ ifneq ("$(wildcard project-conf.h)","") ...@@ -65,7 +69,7 @@ ifneq ("$(wildcard project-conf.h)","")
CFLAGS += -DPROJECT_CONF_PATH=\"project-conf.h\" CFLAGS += -DPROJECT_CONF_PATH=\"project-conf.h\"
endif endif
MODULES += os os/net os/net/mac os/net/mac/framer os/net/routing os/storage MODULES += os/net os/net/mac os/net/mac/framer os/net/routing os/storage
define oname define oname
${patsubst %.c,%.o, \ ${patsubst %.c,%.o, \
...@@ -223,20 +227,27 @@ else ifeq ($(MAKE_ROUTING),MAKE_ROUTING_NULLROUTING) ...@@ -223,20 +227,27 @@ else ifeq ($(MAKE_ROUTING),MAKE_ROUTING_NULLROUTING)
MODULES += os/net/routing/nullrouting MODULES += os/net/routing/nullrouting
endif endif
MODULEDIRS = $(MODULES_REL) ${wildcard ${addprefix $(CONTIKI)/, $(MODULES)}} MODULEDIRS = $(MODULES_REL) ${addprefix $(CONTIKI)/, $(MODULES)}
UNIQUEMODULES = $(call uniq,$(MODULEDIRS)) UNIQUEMODULES = $(call uniq,$(MODULEDIRS))
MODULES_SOURCES = ${foreach d, $(MODULEDIRS), ${subst ${d}/,,${wildcard $(d)/*.c}}} MODULES_SOURCES = ${foreach d, $(UNIQUEMODULES), ${subst ${d}/,,${wildcard $(d)/*.c}}}
CONTIKI_SOURCEFILES += $(MODULES_SOURCES) CONTIKI_SOURCEFILES += $(MODULES_SOURCES)
# Include module-specific makefiles # Include module-specific makefiles
MODULES_INCLUDES = ${wildcard ${foreach d, $(MODULEDIRS), $(d)/Makefile.${notdir $(d)}}} MODULES_INCLUDES = ${wildcard ${foreach d, $(UNIQUEMODULES), $(d)/Makefile.${notdir $(d)}}}
include $(MODULES_INCLUDES)
### Perform an immediate expansion of MODULES_INCLUDES and store it in a
### variable. This will allow us to subsequently filter-out module Makefiles
### that were included in the first pass, such that we don't end up including
### them twice.
MODULES_INCLUDED_FIRST_PASS := $(MODULES_INCLUDES)
include $(MODULES_INCLUDED_FIRST_PASS)
# Iterate once more: include the modules added from the previous include. # Iterate once more: include the modules added from the previous include.
# Only works with one level of nested module inclusion. # Only works with one level of nested module inclusion.
include $(MODULES_INCLUDES) include $(filter-out $(MODULES_INCLUDED_FIRST_PASS),$(MODULES_INCLUDES))
# C-include module-specific macros using -imacros # C-include module-specific macros using -imacros
MODULES_IMACROS = ${wildcard ${foreach d, $(MODULEDIRS), $(d)/module-macros.h}} MODULES_IMACROS = ${wildcard ${foreach d, $(UNIQUEMODULES), $(d)/module-macros.h}}
ifneq ($(MODULES_IMACROS),) ifneq ($(MODULES_IMACROS),)
CFLAGS += ${foreach d, $(MODULES_IMACROS), -imacros $(d)} CFLAGS += ${foreach d, $(MODULES_IMACROS), -imacros $(d)}
endif endif
...@@ -279,7 +290,7 @@ CONTIKI_CPU_DIRS_CONCAT = ${addprefix $(CONTIKI_CPU)/, \ ...@@ -279,7 +290,7 @@ CONTIKI_CPU_DIRS_CONCAT = ${addprefix $(CONTIKI_CPU)/, \
CONTIKI_ARCH_DIRS = ${addprefix $(CONTIKI)/, arch} CONTIKI_ARCH_DIRS = ${addprefix $(CONTIKI)/, arch}
SOURCEDIRS = . $(PROJECTDIRS) $(CONTIKI_TARGET_DIRS_CONCAT) $(CONTIKI_ARCH_DIRS) \ SOURCEDIRS = . $(PROJECTDIRS) $(CONTIKI_TARGET_DIRS_CONCAT) $(CONTIKI_ARCH_DIRS) \
$(CONTIKI_CPU_DIRS_CONCAT) $(CONTIKIDIRS) $(MODULEDIRS) $(EXTERNALDIRS) ${dir $(target_makefile)} $(CONTIKI_CPU_DIRS_CONCAT) $(CONTIKIDIRS) $(MODULEDIRS) $(EXTERNALDIRS)
vpath %.c $(SOURCEDIRS) vpath %.c $(SOURCEDIRS)
vpath %.S $(SOURCEDIRS) vpath %.S $(SOURCEDIRS)
...@@ -465,6 +476,9 @@ ifeq ($(findstring $(TARGET),native cooja),) ...@@ -465,6 +476,9 @@ ifeq ($(findstring $(TARGET),native cooja),)
include $(CONTIKI)/Makefile.embedded include $(CONTIKI)/Makefile.embedded
endif endif
### Include Makefile.gcc for GCC specific definitions and actions
include $(CONTIKI)/Makefile.gcc
# Don't treat $(BUILD_DIR_BOARD)/%.$(TARGET) and $(TARGET) as intermediate # Don't treat $(BUILD_DIR_BOARD)/%.$(TARGET) and $(TARGET) as intermediate
# files because for many platforms they are in fact the primary target. # files because for many platforms they are in fact the primary target.
.PRECIOUS: $(BUILD_DIR_BOARD)/%.$(TARGET) %.$(TARGET) .PRECIOUS: $(BUILD_DIR_BOARD)/%.$(TARGET) %.$(TARGET)
......
# Contiki-NG: The OS for Next Generation IoT Devices <img src="https://github.com/contiki-ng/contiki-ng.github.io/blob/master/images/logo/Contiki_logo_2RGB.png" alt="Logo" width="256">
This version of Contiki-NG is used within the Vela-Lab project and it is customized for that. # Contiki-NG: The OS for Next Generation IoT Devices
[![Build Status](https://travis-ci.org/contiki-ng/contiki-ng.svg?branch=master)](https://travis-ci.org/contiki-ng/contiki-ng/branches) [![Build Status](https://travis-ci.org/contiki-ng/contiki-ng.svg?branch=master)](https://travis-ci.org/contiki-ng/contiki-ng/branches)
[![license](https://img.shields.io/badge/license-3--clause%20bsd-brightgreen.svg)](https://github.com/contiki-ng/contiki-ng/blob/master/LICENSE.md) [![license](https://img.shields.io/badge/license-3--clause%20bsd-brightgreen.svg)](https://github.com/contiki-ng/contiki-ng/blob/master/LICENSE.md)
......
...@@ -10,6 +10,7 @@ CC = arm-none-eabi-gcc ...@@ -10,6 +10,7 @@ CC = arm-none-eabi-gcc
CPP = arm-none-eabi-cpp CPP = arm-none-eabi-cpp
LD = arm-none-eabi-gcc LD = arm-none-eabi-gcc
AR = arm-none-eabi-ar AR = arm-none-eabi-ar
AS = arm-none-eabi-gcc
OBJCOPY = arm-none-eabi-objcopy OBJCOPY = arm-none-eabi-objcopy
OBJDUMP = arm-none-eabi-objdump OBJDUMP = arm-none-eabi-objdump
NM = arm-none-eabi-nm NM = arm-none-eabi-nm
...@@ -25,6 +26,11 @@ ifeq ($(WERROR),1) ...@@ -25,6 +26,11 @@ ifeq ($(WERROR),1)
CFLAGS += -Werror CFLAGS += -Werror
endif endif
### Pass CFLAGS along to assembly files in the build
ASFLAGS += $(CFLAGS)
### Specify '-c' option to assemble only and not link
ASFLAGS += -c
LDFLAGS += -mthumb -mlittle-endian LDFLAGS += -mthumb -mlittle-endian
OBJDUMP_FLAGS += --disassemble --source --disassembler-options=force-thumb OBJDUMP_FLAGS += --disassemble --source --disassembler-options=force-thumb
......
/*
* Copyright (c) 2019, Toshiba Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup arm
*
* Arm Cortex-M implementation of atomic operations using the LDREX,
* STREX and DMB instructions.
*
* @{
*/
#ifndef ATOMIC_CORTEX_H_
#define ATOMIC_CORTEX_H_
#include <contiki.h>
#ifdef CMSIS_CONF_HEADER_PATH
#include CMSIS_CONF_HEADER_PATH
#endif
#include <stdint.h>
#include <stdbool.h>
#define atomic_cas_uint8(t,o,n) atomic_cortex_cas_uint8((t),(o),(n))
static inline bool
atomic_cortex_cas_uint8(uint8_t *target, uint8_t old_val, uint8_t new_val)
{
int status = 1;
if(__LDREXB(target) == old_val) {
status = __STREXB(new_val, target);
}
__DMB();
return status == 0 ? true : false;
}
#endif /* ATOMIC_CORTEX_H_ */
/** @} */
...@@ -263,6 +263,11 @@ ...@@ -263,6 +263,11 @@
#ifndef NETSTACK_CONF_RADIO #ifndef NETSTACK_CONF_RADIO
#define NETSTACK_CONF_RADIO cc2538_rf_driver #define NETSTACK_CONF_RADIO cc2538_rf_driver
#endif #endif
/**
* \brief Maximum packet size
*/
#define cc2538_rf_driver_max_payload_len 125
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
......
...@@ -65,11 +65,14 @@ ...@@ -65,11 +65,14 @@
/* Path to CMSIS header */ /* Path to CMSIS header */
#define CMSIS_CONF_HEADER_PATH "cc2538_cm3.h" #define CMSIS_CONF_HEADER_PATH "cc2538_cm3.h"
/* Path to headers with implementation of mutexes and memory barriers */ /* Path to headers with implementation of mutexes, atomic and memory barriers */
#define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h" #define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h"
#define ATOMIC_CONF_ARCH_HEADER_PATH "atomic-cortex.h"
#define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h" #define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h"
/*---------------------------------------------------------------------------*/
#define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h" #define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h"
#define GPIO_HAL_CONF_ARCH_SW_TOGGLE 1
#define GPIO_HAL_CONF_PORT_PIN_NUMBERING 0
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#endif /* CC2538_DEF_H_ */ #endif /* CC2538_DEF_H_ */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
...@@ -600,6 +600,10 @@ prepare(const void *payload, unsigned short payload_len) ...@@ -600,6 +600,10 @@ prepare(const void *payload, unsigned short payload_len)
{ {
uint8_t i; uint8_t i;
if(payload_len > NETSTACK_RADIO_MAX_PAYLOAD_LEN) {
return RADIO_TX_ERR;
}
LOG_INFO("Prepare 0x%02x bytes\n", payload_len + CHECKSUM_LEN); LOG_INFO("Prepare 0x%02x bytes\n", payload_len + CHECKSUM_LEN);
/* /*
...@@ -661,6 +665,10 @@ transmit(unsigned short transmit_len) ...@@ -661,6 +665,10 @@ transmit(unsigned short transmit_len)
LOG_INFO("Transmit\n"); LOG_INFO("Transmit\n");
if(transmit_len > NETSTACK_RADIO_MAX_PAYLOAD_LEN) {
return RADIO_TX_ERR;
}
if(!(rf_flags & RX_ACTIVE)) { if(!(rf_flags & RX_ACTIVE)) {
t0 = RTIMER_NOW(); t0 = RTIMER_NOW();
on(); on();
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
#include <stdint.h> #include <stdint.h>
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg) gpio_hal_arch_no_port_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
{ {
uint8_t port, pin_num, pin_mask; uint8_t port, pin_num, pin_mask;
uint32_t port_base; uint32_t port_base;
...@@ -94,7 +94,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg) ...@@ -94,7 +94,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
gpio_hal_pin_cfg_t gpio_hal_pin_cfg_t
gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin) gpio_hal_arch_no_port_pin_cfg_get(gpio_hal_pin_t pin)
{ {
uint8_t port, pin_num, pin_mask; uint8_t port, pin_num, pin_mask;
uint32_t port_base; uint32_t port_base;
...@@ -145,17 +145,17 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin) ...@@ -145,17 +145,17 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_write_pin(gpio_hal_pin_t pin, uint8_t value) gpio_hal_arch_no_port_write_pin(gpio_hal_pin_t pin, uint8_t value)
{ {
if(value == 1) { if(value == 1) {
gpio_hal_arch_set_pin(pin); gpio_hal_arch_set_pin(GPIO_HAL_NULL_PORT, pin);
return; return;
} }
gpio_hal_arch_clear_pin(pin); gpio_hal_arch_clear_pin(GPIO_HAL_NULL_PORT, pin);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_set_pins(gpio_hal_pin_mask_t pins) gpio_hal_arch_no_port_set_pins(gpio_hal_pin_mask_t pins)
{ {
GPIO_SET_PIN(GPIO_A_BASE, pins & 0xFF); GPIO_SET_PIN(GPIO_A_BASE, pins & 0xFF);
GPIO_SET_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF); GPIO_SET_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF);
...@@ -164,7 +164,7 @@ gpio_hal_arch_set_pins(gpio_hal_pin_mask_t pins) ...@@ -164,7 +164,7 @@ gpio_hal_arch_set_pins(gpio_hal_pin_mask_t pins)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_clear_pins(gpio_hal_pin_mask_t pins) gpio_hal_arch_no_port_clear_pins(gpio_hal_pin_mask_t pins)
{ {
GPIO_CLR_PIN(GPIO_A_BASE, pins & 0xFF); GPIO_CLR_PIN(GPIO_A_BASE, pins & 0xFF);
GPIO_CLR_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF); GPIO_CLR_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF);
...@@ -173,7 +173,7 @@ gpio_hal_arch_clear_pins(gpio_hal_pin_mask_t pins) ...@@ -173,7 +173,7 @@ gpio_hal_arch_clear_pins(gpio_hal_pin_mask_t pins)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
gpio_hal_pin_mask_t gpio_hal_pin_mask_t
gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins) gpio_hal_arch_no_port_read_pins(gpio_hal_pin_mask_t pins)
{ {
gpio_hal_pin_mask_t rv = 0; gpio_hal_pin_mask_t rv = 0;
...@@ -186,7 +186,8 @@ gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins) ...@@ -186,7 +186,8 @@ gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_write_pins(gpio_hal_pin_mask_t pins, gpio_hal_pin_mask_t value) gpio_hal_arch_no_port_write_pins(gpio_hal_pin_mask_t pins,
gpio_hal_pin_mask_t value)
{ {
GPIO_WRITE_PIN(GPIO_A_BASE, pins & 0xFF, value & 0xFF); GPIO_WRITE_PIN(GPIO_A_BASE, pins & 0xFF, value & 0xFF);
GPIO_WRITE_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF, (value >> 8) & 0xFF); GPIO_WRITE_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF, (value >> 8) & 0xFF);
......
...@@ -58,31 +58,31 @@ ...@@ -58,31 +58,31 @@
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#define gpio_hal_arch_init() do { /* Do nothing */ } while(0) #define gpio_hal_arch_init() do { /* Do nothing */ } while(0)
#define gpio_hal_arch_interrupt_enable(p) do { \ #define gpio_hal_arch_interrupt_enable(port, p) do { \
GPIO_ENABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \ GPIO_ENABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
NVIC_EnableIRQ(PIN_TO_PORT(p)); \ NVIC_EnableIRQ(PIN_TO_PORT(p)); \
} while(0); } while(0);
#define gpio_hal_arch_interrupt_disable(p) \ #define gpio_hal_arch_interrupt_disable(port, p) \
GPIO_DISABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) GPIO_DISABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
#define gpio_hal_arch_pin_set_input(p) do { \ #define gpio_hal_arch_pin_set_input(port, p) do { \
GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \ GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
GPIO_SET_INPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \ GPIO_SET_INPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
} while(0); } while(0);
#define gpio_hal_arch_pin_set_output(p) do { \ #define gpio_hal_arch_pin_set_output(port, p) do { \
GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \ GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
GPIO_SET_OUTPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \ GPIO_SET_OUTPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
} while(0); } while(0);
#define gpio_hal_arch_set_pin(p) \ #define gpio_hal_arch_set_pin(port, p) \
GPIO_SET_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) GPIO_SET_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
#define gpio_hal_arch_clear_pin(p) \ #define gpio_hal_arch_clear_pin(port, p) \
GPIO_CLR_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) GPIO_CLR_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
#define gpio_hal_arch_read_pin(p) \ #define gpio_hal_arch_read_pin(port, p) \
(GPIO_READ_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) == 0 ? 0 : 1) (GPIO_READ_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) == 0 ? 0 : 1)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#endif /* GPIO_HAL_ARCH_H_ */ #endif /* GPIO_HAL_ARCH_H_ */
......
...@@ -1114,13 +1114,8 @@ ep_tx(uint8_t ep_hw) ...@@ -1114,13 +1114,8 @@ ep_tx(uint8_t ep_hw)
len -= copy; len -= copy;
ep->buffer->left -= copy; ep->buffer->left -= copy;
/* /* Delay somewhat if the previous packet has not yet left the IN FIFO */
* Delay somewhat if the previous packet has not yet left the IN FIFO, while(REG(USB_CSIL) & USB_CSIL_INPKT_RDY);
* making sure the dog doesn't bark while we're waiting
*/
while(REG(USB_CSIL) & USB_CSIL_INPKT_RDY) {
watchdog_periodic();
}
write_hw_buffer(EP_INDEX(ep_hw), ep->buffer->data, copy); write_hw_buffer(EP_INDEX(ep_hw), ep->buffer->data, copy);
ep->buffer->data += copy; ep->buffer->data += copy;
......
...@@ -97,4 +97,4 @@ else ...@@ -97,4 +97,4 @@ else
endif endif
### For the login etc targets ### For the login etc targets
BAUDRATE = 115200 BAUDRATE ?= 115200
...@@ -100,13 +100,18 @@ ...@@ -100,13 +100,18 @@
#define CSMA_CONF_SEND_SOFT_ACK 0 #define CSMA_CONF_SEND_SOFT_ACK 0
#endif /* CC13XX_CONF_PROP_MODE */ #endif /* CC13XX_CONF_PROP_MODE */
#define NETSTACK_RADIO_MAX_PAYLOAD_LEN 125
/* Platform-specific (H/W) AES implementation */ /* Platform-specific (H/W) AES implementation */
#ifndef AES_128_CONF #ifndef AES_128_CONF
#define AES_128_CONF cc26xx_aes_128_driver #define AES_128_CONF cc26xx_aes_128_driver
#endif /* AES_128_CONF */ #endif /* AES_128_CONF */
/* This is fixed */
#define ieee_mode_driver_max_payload_len 125
/* This maybe changed in the future, with software upgrade */
#define prop_mode_driver_max_payload_len 125
/* This is not used, but needs to be defined in order to compile */
#define ble_cc2650_driver_max_payload_len 125
/** @} */ /** @} */
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** /**
......
...@@ -133,13 +133,14 @@ ...@@ -133,13 +133,14 @@
/* Path to CMSIS header */ /* Path to CMSIS header */
#define CMSIS_CONF_HEADER_PATH "cc13x0-cc26x0-cm3.h" #define CMSIS_CONF_HEADER_PATH "cc13x0-cc26x0-cm3.h"
/* Path to headers with implementation of mutexes and memory barriers */ /* Path to headers with implementation of mutexes, atomic and memory barriers */
#define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h" #define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h"
#define ATOMIC_CONF_ARCH_HEADER_PATH "atomic-cortex.h"
#define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h" #define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h"
#define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h"
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#define GPIO_HAL_CONF_ARCH_SW_TOGGLE 0 #define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h"
#define GPIO_HAL_CONF_ARCH_SW_TOGGLE 0
#define GPIO_HAL_CONF_PORT_PIN_NUMBERING 0
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#define SPI_CONF_CONTROLLER_COUNT 2 #define SPI_CONF_CONTROLLER_COUNT 2
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
......
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
#define CONFIG_MASK (IOC_IOPULL_M | IOC_INT_M | IOC_IOMODE_OPEN_SRC_INV) #define CONFIG_MASK (IOC_IOPULL_M | IOC_INT_M | IOC_IOMODE_OPEN_SRC_INV)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg) gpio_hal_arch_no_port_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
{ {
uint32_t config; uint32_t config;
gpio_hal_pin_cfg_t tmp; gpio_hal_pin_cfg_t tmp;
...@@ -86,7 +86,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg) ...@@ -86,7 +86,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
gpio_hal_pin_cfg_t gpio_hal_pin_cfg_t
gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin) gpio_hal_arch_no_port_pin_cfg_get(gpio_hal_pin_t pin)
{ {
gpio_hal_pin_cfg_t cfg; gpio_hal_pin_cfg_t cfg;
uint32_t tmp; uint32_t tmp;
...@@ -129,7 +129,7 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin) ...@@ -129,7 +129,7 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
gpio_hal_pin_mask_t gpio_hal_pin_mask_t
gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins) gpio_hal_arch_no_port_read_pins(gpio_hal_pin_mask_t pins)
{ {
gpio_hal_pin_mask_t oe_pins; gpio_hal_pin_mask_t oe_pins;
...@@ -143,7 +143,7 @@ gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins) ...@@ -143,7 +143,7 @@ gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins)
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
uint8_t uint8_t
gpio_hal_arch_read_pin(gpio_hal_pin_t pin) gpio_hal_arch_no_port_read_pin(gpio_hal_pin_t pin)
{ {
if(ti_lib_gpio_get_output_enable_dio(pin)) { if(ti_lib_gpio_get_output_enable_dio(pin)) {
return (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) >> pin) & 1; return (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) >> pin) & 1;
......
...@@ -54,21 +54,21 @@ ...@@ -54,21 +54,21 @@
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
#define gpio_hal_arch_init() do { /* Do nothing */ } while(0) #define gpio_hal_arch_init() do { /* Do nothing */ } while(0)